Quantum Computing and Reversible Circuits (Select Publications)
H. Thapliyal, E. Munoz-Coreas, T.S.S. Varun, and T. S. Humble, “Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth”, Accepted in IEEE Transactions on Emerging Topics in Computing, 2019.
T.S. Humble, H. Thapliyal, E. Muñoz-Coreas, F.A. Mohiyaddin, and R.S. Bennink, “Quantum computing circuits and devices”, Accepted in IEEE Design and Test, 2019.
E. Munoz-Coreas and H. Thapliyal, “Quantum Circuit Design of A T-count Optimized Integer Multiplier,” IEEE Transactions on Computers, DOI: 10.1109/TC.2018.2882774, (Date of Publication: 22 November 2018).
E. Munoz-Coreas and H. Thapliyal, “T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 14 Issue 3, October 2018. Article No.: 36 doi>10.1145/3264816
E. Munoz-Coreas and H. Thapliyal, “T-count Optimized Quantum Circuits for Bilinear Interpolation”, Proceedings of the International Green and Sustainable Computing Conference (IGSC’18), Pittsburgh, October 2018.
H. Thapliyal, T. S. S. Varun, E. Munoz-Coreas, K. A. Britt, and T. S. Humble, “Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth,” in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017, pp. 123–128.
E. Munoz-Coreas, and H. Thapliyal, “Design of Quantum Circuits for Galois Field Squaring and Exponentiation”, Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, July 2017, pp. 68-73.
H. V. Jayashree, H. Thapliyal et al., “Efficient Circuit Design of Reversible Square,” Transactions on Computational Science XXIX, pp 33-46, March 2017.
M. H. A. Khan, H. Thapliyal, and E. Munoz-Coreas, “Automatic synthesis of quaternary quantum circuits,” The Journal of Supercomputing, Sep. 2016. DOI: 10.1007/s11227-016-1878-5
H. Thapliyal, “Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates,” in Transactions on Computational Science XXVII, M. L. Gavrilova and C. J. K. Tan, Eds. Springer Berlin Heidelberg, 2016, pp. 10–34.
S. Kotiyal and H. Thapliyal, “Design Methodologies for Reversible Logic Based Barrel Shifters,” Journal of Circuits, Systems and Computers, vol. 25, no. 02, p. 1650003, Feb. 2016.
H. V. Jayashree, H. Thapliyal, H. R. Arabnia, and V. K. Agrawal, “Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier,” The Journal of Supercomputing, vol. 72, no. 4, pp. 1477–1493, Apr. 2016.
S. Kotiyal, H. Thapliyal and N. Ranganathan, “Reversible logic based multiplication computing unit using binary tree data structure”, The Journal of Supercomputing, vol. 71, no. 7, pp. 2668–2693, Mar. 2015
S. Kotiyal, H. Thapliyal and N. Ranganathan, “Design of Reversible Adder-Subtractor and Its Mapping In Optical Computing Domain”, Springer Transactions on Computational Science XXIV Lecture Notes in Computer Science, Vol. 8911, Jan 2015
S. Kotiyal, H. Thapliyal and N. Ranganathan, “Efficient reversible NOR gates and their mapping in optical computing domain”, Microelectronics Journal, Vol. 45, No.6, pp. 825-834, June 2014.
H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal of Emerging Technologies in Computing Systems,Vol.9, No.3,pp. 17:1–17:31, Sep 2013.
H. Thapliyal, N. Ranganathan and S.Kotiyal, “Design of Testable Reversible Sequential Circuits “, IEEE Transactions on VLSI, vol. 21, no.7, pp.1201-1209, July 2013
H.Thapliyal et al., “Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder”, Springer Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97
H. Thapliyal and N. Ranganathan, “Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay and Garbage Outputs”, ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, No. 4, Article 14, Dec 2010
H. Thapliyal and N. Ranganathan, “Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, IEEE Transactions on Nanotechnology, vol. 9, No. 1, pp. 62-69, Jan 2010.
H. Thapliyal et al., “Efficient Reversible Logic Design of BCD Subtractors”, Springer Transactions on Computational Sciences Journal, Vol. 3, LNCS 5300, pp. 99-121, 2009.